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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr21v1410 1-ch full-speed usb uart april 2012 rev. 1.3.0 general description the xr21v1410 (v1410) is an enhanced universal asynchronous receiver and transmitter (uart) with a usb interface. the usb interface is fully complia nt to full speed usb 2.0 specification that supports 1 2 mbps usb data transfer rate. the usb interface also supports usb suspend, resume and remote wakeup operations. the v1410 operates from an internal 48mhz clock therefore no external crystal/oscillator is require d like previous generation uarts. with the fractional baud rate generator, any baud rate can accurately be generated using the internal 48mhz clock. the large 128-byte tx fifo and 384-byte rx fifo of the v1410 helps to optimize the overall data throughput for various applications. the automatic transceiver direction control feature simplifies bo th the hardware and software for half-duplex rs-485 applications. if required, the multidrop (9-bit) mo de with automatic half-duplex transceiver control feat ure further simplifies typical multidrop rs-485 applications. the v1410 operates from a single 2.97 to 3.63 volt power supply and has 5v tolerant inputs. the v1410 is available in a 16-pin qfn package. whql certified software drivers for windows 2000, xp, vista, 7 and ce, as well as linux and mac are supported for the xr21v1410. applications portable appliances external converters (dongles) battery-operated devices cellular data devices factory automation and process controls industrial applications features usb 2.0 compliant, full-speed (12 mbps) n supports usb suspend, resume and remote wakeup operations enhanced uart features n data rates up to 12 mbps n fractional baud rate generator n 128 byte tx fifo n 384 byte rx fifo n 7, 8 or 9 data bits n 1 or 2 stop bits n odd, even, mark, space, or no parity n automatic hardware (rts/cts or dtr/dsr) flow control n automatic software (xon/xoff) flow control n multidrop mode n auto transceiver enable n half-duplex mode n selectable gpio or modem i/o internal 48 mhz clock single 2.97-3.63v power supply 5v tolerant inputs 16-pin qfn package virtual com port whql certified drivers n windows 2000, xp, vista and win7 n windows ce 4.2, 5.0, 6.0 n linux n mac
xr21v1410 2 1-ch full-speed usb uart rev. 1.3.0 n ote : tr = tape and reel, f = green / rohs f igure 1. xr21v1410 b lock d iagram f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus XR21V1410IL16-F 16-pin qfn -40c to +85c active xr21v1410il16tr-f 16-pin qfn -40c to +85c active usb slave interface 128-byte tx fifo gpios/ modem io tx rx internal 48mhz oscillator usbd+ usbd- 384-byte rx fifo gpio5/rts# gpio4/cts# gpio3/dtr# gpio2/dsr# gpio1/cd# gpio0/ri#/rwk# uart fractional brg internal status and control registers 3.3v vcc gnd i 2 c interface sda scl 16-pin qfn 1 2 3 4 gpio5/rts# gpio4/cts# lowpower gnd 5 86 7 gpio1/cd# gpio0/ri#/rwk# gpio2/dsr# gpio3/dtr# 12 11 10 9 16 13 15 14 usbd- gnd usbd+ vcc rx tx sda scl
xr21v1410 3 rev. 1.3.0 1-ch full-speed usb uart pin descriptions pin description n ame 16-qfn p in # t ype d escription uart signals rx 10 i uart channel a receive data or ir receive data. thi s pin has an internal pull-up resistor. internal pull-up resisto r is not disabled during suspend mode. tx 9 o uart channel a transmit data or ir transmit data. gpio0/ri#/rwk# 8 i/o general purpose i/o or uart ring-indicator input (a ctive low) or remote wakeup input. see section 1.5.11, remote wakeup on page 10 . this pin has an internal pull-up resistor which is disabled during suspend mode. if using this gpio as an input, an external pull-up resistor is required to minimize the device power consumption i n the suspend mode. gpio1/cd# 7 i/o general purpose i/o or uart carrier-detect input (a ctive low). this pin has an internal pull-up resistor which is disabled during suspend mode. if using this gpio as an input, an external pull-up resistor is required to minimize the device power consumption in the suspen d mode. gpio2/dsr# 6 i/o general purpose i/o or uart data-set-ready input (a ctive low). see section 1.5.5, automatic dtr/dsr hardware flow con trol on page 9. this pin has an internal pull-up resistor which is disabled during suspend mode. if using this gpio as an input, an external pull-up resistor is required to minimize the device power consumption i n the suspend mode. gpio3/dtr# 5 i/o general purpose i/o or uart data-terminal-ready out put (active low). see section 1.5.5, automatic dtr/dsr hardware flow con- trol on page 9. this pin has an internal pull-up resistor which is disabled during suspend mode. if using this gpio as an input, an external pull-up resistor is required to minimize the device power consumption i n the suspend mode. gpio4/cts# 4 i/o general purpose i/o or uart clear-to-send input (ac tive low). see section 1.5.4, automatic rts/cts hardware flow con trol on page 8. this pin has an internal pull-up resistor which is disabled during suspend mode. if using this gpio as an input, an external pull-up resistor is required to minimize the device power consumption i n the suspend mode. gpio5/rts# 3 i/o general purpose i/o or uart request-to-send output (active low). see section 1.5.4, automatic rts/cts hardware flow con- trol on page 8. this pin has an internal pull-up resistor which is disabled during suspend mode. if using this gpio as an input, an external pull-up resistor is required to minimize the device power consumption i n the suspend mode.
xr21v1410 4 1-ch full-speed usb uart rev. 1.3.0 n ote : pin type: i=input, o=output, i/o= input/output, od= output open drain. usb interface signals usbd+ 15 i/o usb port differential data plus. this pin has a 1.5 k ohm internal pull-up. usbd- 14 i/o usb port differential data minus. i 2 c interface signals sda 11 i/o od i 2 c-controller data input/output (open-drain). an op tional external i 2 c eeprom can be used to store default configurations upon power-up including the usb vendor id and device id. see table 3 . a pull-up resistor (typically 4.7 to 10 kohms) is required. if an eeprom is not used, this pin can be used with the scl pin to select the remote wake-up and power modes. an exte rnal pull-up or pull-down resistor is required. see table 2 scl 12 i/o od i 2 c-controller serial input clock. an optional exter nal i 2 c eeprom can be used to store default configurations upon power- up including the usb vendor id and device id. see table 3 . a pull-up resistor (typically 4.7 to 10 kohms) is required. if an eeprom is not used, this pin can be used with the sda pin to select the remote wake-up and power modes. an exter nal pull-up or pull-down resistor is required. see table 2 miscellaneous signals lowpower 2 o low power status output. the lowpower pin will be asserted when- ever it is not safe to draw the amount of current f rom vbus power requested in the device max power field of the conf iguration descriptor. the lowpower pin will behave differently for a low power device and a high power device. low-power device (<= 1 unit load or 100 ma i.e. bma xpower <= 0x32): lowpower pin is asserted when the usb uart is in su spend mode. high-power deivce (bmaxpower > 0x32): lowpower pin is asserted when the usb uart is in suspend mode or wh en it is not yet configured. the lowpower pin will be de-asserted whenever it is safe to draw the amount of current requested in the device maximum p ower field. this pin is sampled momentarily at power-up or at a ny usb bus reset to configure the polarity of the lowpower output durin g suspend mode. an external (10k) pull-up resistor will cause the l owpower pin to be asserted high during suspend mode. an external (3.3 k) pull-down resis- tor will cause the lowpower pin to be asserted low during suspend mode. vcc 16 pwr +3.3v power supply. (note that all device inputs a re 5v tolerant.) gnd 1, 13 pwr power supply common, ground. pin description n ame 16-qfn p in # t ype d escription
xr21v1410 5 rev. 1.3.0 1-ch full-speed usb uart 1.0 functional descriptions 1.1 usb interface the usb interface of the v1410 is compliant with th e usb 2.0 full-speed specifications. the usb configuration model presented by the v1410 to the d evice driver is compatible to the abstract control model of the usb communication device class (cdc-acm). the v1410 uses the following set of parameters: 1 control endpoint n endpoint 0 as outlined in the usb specifications 1 configuration is supported 2 interfaces for the uart channel n single interrupt endpoint n bulk-in and bulk-out endpoints 1.1.1 usb vendor id exars usb vendor id is 0x04e2. this is the defaul t vendor id that is used for the v1410 unless a val id eeprom is present on the i 2 c interface signals. if a valid eeprom is present, the vendor id from the eeprom will be used. 1.1.2 usb product id the default usb product id for the v1410 is 0x1410. if a valid eeprom is present, the product id from the eeprom will be used. 1.2 usb device driver the v1410 device can be used with either a standard cdc-acm driver or a custom driver. when the cdc- acm driver is used, the driver has no knowledge of the v1410 device registers. because of this, the v1410 device is initialized to the following settings: note that when using a cdc-acm driver, the v1410 wi ll automatically change the bmaxpacketsize to 63 by tes to compensate for a known issue with the microsoft cdc-acm device driver. a register is available to change this setting with a custom driver as well. see section 3.4.1, custom register description (read/w rite) on page 22 and section 1.5.2.1, wide mode receive on page 7 . t able 1: v1410 r egister d efaults with cdc-acm d river r egister v alue n otes flow_control 0x01 hardware flow control gpio_mode 0x01 rts / cts flow control gpio_direction 0x08 dtr configured as an output (in a ddition to rts which is set by gpio_mode) gpio_int_mask 0x30 cd and dsr are interrupt sensitive , i.e. can cause a usb inter- rupt to be generated
xr21v1410 6 1-ch full-speed usb uart rev. 1.3.0 1.3 i 2 c interface the i 2 c interface provides connectivity to an external i 2 c memory device (i.e. eeprom) that can be read by the v1410 for configuration. the sda and scl are used to specify whether remote wakeup and/or bus powered configurations are to be supported. these pins are sampled at power-up. th e following table describes how remote wakeup and b us powered support. 1.3.1 eeprom contents the i 2 c address should be 0xa0. an eeprom can be used to override default vendor ids and device ids, as well as other attributes and maximum power consumpt ion. the eeprom must contain 8 bytes of data as specified in table 3 these values are uploaded from the eeprom to the co rresponding usb standard device descriptor or standard configuration descriptor. for details of the usb descriptors, refer to the usb 2.0 specifica tions. 1.3.1.1 vendor id the vendor id value replaces the idvendor field in the usb standard device descriptor. 1.3.1.2 product id the product id value replaces the idproduct field i n the usb standard device descriptor. 1.3.1.3 device attributes the device attributes value replaces the bmattribut es field in the usb standard configuration descript or. the default setting in the v1410 device is 0xa0. the b it field definitions are: bit 7 is reserved - set to 1 t able 2: r emote w akeup and p ower m odes sda scl r emote w ake - up s upport p ower m ode 1 1 no self-powered 1 0 no bus-powered 0 1 yes self-powered 0 0 yes bus-powered t able 3: eeprom c ontents eeprom a ddress c ontents 0 vendor id (lsb) 1 vendor id (msb) 2 product id (lsb) 3 product id (msb) 4 device attributes 5 device maximum power 6 reserved 7 signature of 0x58 (x). if the signature is not correct, the contents of the eeprom are ignored.
xr21v1410 7 rev. 1.3.0 1-ch full-speed usb uart bit 6 is self-powered mode - set to 0 for bus-pow ered, set to 1 for self-powered bit 5 is remote wakeup support - set to 0 for no support, set to 1 for remote wakeup support bit 4:0 are reserved - set to 0 1.3.1.4 device maximum power the device maximum power value replaces the bmaxpow er field in the usb standard configuration descriptor. the value specified is in units of 2 m a. for example, the value 0x2f is decimal 47 or 94 ma. note that the default bmaxpower of the v1410 device is 9 4 ma. 1.4 uart manager the uart manager enables/disables the uart includin g the tx and rx fifos. the uart manager is located in a separate register block from the uart registers. 1.5 uart the uart can be configured via usb control transfer s from the usb host. the uart transmitter and rece iver sections are described seperately in the following sections. at power-up, the v1410 will default to 9600 bps, 8 data bits, no parity bit, 1 stop bit, and no flow c ontrol. if a standard cdc driver accesses the v141 0, defaults will change. see section 1.2, usb device driver on page 5. 1.5.1 transmitter the transmitter consists of a 128-byte tx fifo and a transmit shift register (tsr). once a bulk-out p acket has been received and the crc has been validated, t he data bytes in that packet are written into the t x fifo of the specified uart channel. data from the tx fi fo is transferred to the tsr when the tsr is idle o r has completed sending the previous data byte. the tsr shifts the data out onto the tx output pin at the d ata rate defined by the clock_divisor and tx_clock_mask regi sters. the transmitter sends the start bit followed by the data bits (starting with the lsb), inserts the proper parity-bit if enabled, and adds the stop- bit(s). the transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity. if 9 bit data is selected without wide mode, the 9t h bit will always be 0. 1.5.1.1 wide mode transmit when both 9 bit data and wide mode are enabled, two bytes of data must be written. the first byte tha t is loaded into the tx fifo are the first 8 bits (data bits 7-0) of the 9-bit data. bit-0 of the second b yte that is loaded into the tx fifo is bit-8 of the 9-bit data. the data that is transmitted on the tx pin is as follows: start bit, 9-bit data, stop bit. use the wide_mode regis ter to enable wide mode. 1.5.2 receiver the receiver consists of a 384-byte rx fifo and a r eceive shift register (rsr). data that is received in the rsr via the rx pin is transferred into the rx fifo along with any error tags such as framing, parity, break and overrun errors. data from the rx fifo can be s ent to the usb host by sending a bulk-in packet. if the wide mode is not enabled, then 7 or 8 bits o f data and optionally a parity bit are transferred to the usb host. 1.5.2.1 wide mode receive in wide mode, the v1410 receives a 7, 8 or 9 bit ch aracter and then forwards the character along with 3 associated error bits to the usb host in two bytes. if data is 7 or 8 bits, a parity bit is also recei ved and checked if enabled. if data is 9 bits, no parity is checked . the 9th bit of data is in bit position 0 along wi th the 3 error bits, break, frame error and overrun error flags in bit p ositions 1, 2 & 3 respectively. in wide mode, the p arity and framing error and break flag are associated with th e character that they accompany and the overrun err or is tied to the current contents of the entire rx fifo.
xr21v1410 8 1-ch full-speed usb uart rev. 1.3.0 f igure 3. r eceive d ata f ormat error flags are also available from the error_statu s register and the interrupt packet, however these flags are historical flags indicating that an error has o ccurred since the previous read of the status regis ter. therefore, no conclusion can be drawn as to which s pecific byte(s) may have contained an actual error in this manner. 1.5.3 gpio there are 6 gpios. by default, the gpios are gener al purpose i/os. however, there are few modes that can be enabled to add additional feature such as auto r ts/cts flow control, auto dtr/dsr flow control or transceiver enable control. see table 14 . 1.5.4 automatic rts/cts hardware flow control gpio5 and gpio4 of the uart channel can be enabled as the rts# and cts# signals for auto rts/cts flow control when gpio_mode[2:0] = 001 and flow_c ontrol[2:0] = 001. automatic rts flow control is used to prevent data overrun errors in local rx fif o by de-asserting the rts signal to the remote uart . when there is room in the rx fifo, the rts pin will be re-asserted. automatic cts flow control is use d to prevent data overrun to the remote rx fifo. the cts # input is monitored to suspend/restart the local transmitter (see figure 4 ): 1st byte 2nd byte 9 bit mode 7 6 5 4 3 2 1 0 x x x x o f b p 1st byte b = break f = framing error o = overrun error 2nd byte 7 or 8 bit mode p = parity error (= 0 if not enabled) 7 = 0 in 7 bit mode x = 0 7 6 5 4 3 2 1 0 x x x x o f b 8 b = break f = framing error o = overrun error x = 0
xr21v1410 9 rev. 1.3.0 1-ch full-speed usb uart 1.5.5 automatic dtr/dsr hardware flow control auto dtr/dsr hardware flow control behaves the same as the auto rts/cts hardware flow control described above except that it uses the dtr# and ds r# signals. for auto hardware flow control, flow_control[2:0] = 001. gpio3 and gpio2 become dtr# and dsr#, respectively, when gpio_mode[2:0] = 010. 1.5.6 automatic xon/xoff software flow control when software flow control is enabled, the v1410 co mpares the receive data characters with the program med xon or xoff characters. if the received character m atches the programmed xoff character, the v1410 wil l halt transmission as soon as the current character has c ompleted transmission. data transmission is resumed when a received character matches the xon character . software flow control is enabled when flow_control[2:0] = 010. 1.5.7 multidrop mode with address matching the v1410 device has two address matching modes whi ch are also set by the flow control register using modes 3 and 4. these modes are intended for a multi -drop network application. in these modes, the xon_char register holds a unicast address and the x off_char holds a multicast address. a unicast address is used by a transmitting master to broadca st an address to all attached slave devices that is intended for only one slave device. a multicast address is u sed to broadcast an address intended for more than one recipient device. each attached slave device should have a unique unicast address value stored in the xon_char register, while multiple slaves may have t he same multicast adderss stored in the xoff_char register. an address match occurs when an address b yte (9th bit or parity bit is 1) is received that matches the value stored in either the xon_char or xoff_char re gister. f igure 4. a uto rts and cts f low c ontrol o peration rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr21v1410 10 1-ch full-speed usb uart rev. 1.3.0 1.5.7.1 receiver if an address match occurs in either flow control m ode 3 or 4, the address byte will not be loaded int o the rx fifo, but all subsequent data bytes will be loaded into the rx fifo. the uart receiver will automatica lly be disabled when an address byte is received that does not match the values in the xon_char or xoff_char register. 1.5.7.2 transmitter in flow control mode 3, the uart transmitter is alw ays enabled, irrespective of the rx address match. in flow control mode 4, the uart transmitter will only be e nabled if there is an rx address match. 1.5.8 programmable turn-around delay by default, the gpio5/rts# pin will be de-asserted immediately after the stop bit of the last byte has been shifted. however, this may not be ideal for system s where the signal needs to propagate over long cab les. therefore, the de-assertion of gpio5/rts# pin can b e delayed from 1 to 15 bit times via the xcvr_en_delay register to allow for the data to rea ch distant uarts. 1.5.9 half-duplex mode half-duplex mode is enabled when flow_control[3] = 1. in this mode, the uart will ignore any data on the rx input when the uart is transmitting data. 1.5.10 rx fifo latency in normal operation all bulk-in transfers will be o f maxpacketsize (64) bytes to improve throughput an d to minimize usb host processing. however, in cases whe re the baud rate is low this may increase latency unacceptably. to compensate, the v1410 device has a low latency mode in which received data bytes wil l be immediately forwarded at the next bulk_in packet. t he low latency mode will be automatically set from a cdc_acm_if_set_line_coding command whenever the bau d rate is less than 46921 bps or alternately a custom driver may set the rx_fifo_low_latency regis ter bit to force rx data to be delivered without delay. 1.5.11 remote wakeup per usb standard, the v1410 device will begin to en ter the suspend state if it does not detect any act ivity (including sof packets) on its usb data lines for 3 ms. the gpio0/ri#/rwk# pin can be used to request that the host exit the suspend state. a high to low tra nsition on this pin will cause the device to signal a remote wakeup request to the host via a custom driver. no te that the standard cdc-acm driver does not suppor t this feature. in order for the remote wakeup to work, s everal things must be properly configured. first, the gpio0/ ri#/rwk# pin must be configured as an input. additi onally, the v1410 device must have the remote wakeu p feature support indicated in the usb attributes - s ee section 1.3, i2c interface on page 6 . lastly, a custom software driver must inform the usb host tha t the peripheral device supports the remote wake-up feature.
xr21v1410 11 rev. 1.3.0 1-ch full-speed usb uart 2.0 usb control commands the following table shows all of the usb control co mmands that are supported by the v1410. commands included are standard usb commands, cdc-acm command s and custom exar commands. t able 4: s upported usb c ontrol c ommands n ame r equest t ype r equest v alue i ndex l ength d escription dev get_status 0x80 0 0 0 0 0 2 0 device: remote wake-up + self-powered if get_status 0x81 0 0 0 1-4, 129- 132 0 2 0 interface: zero ep get_status 0x82 0 0 0 0-4, 129- 136 0 2 0 endpoint: halted dev clear_feature 0x00 1 1 0 0 0 0 0 device remote wake-up ep clear_feature 0x02 1 0 0 0-4, 129- 136 0 0 0 endpoint halt dev set_feature 0x00 3 1 00 0 0 0 0 device remote wake-up dev set_feature 0x00 3 2 0 0 test 0 0 test mode ep set_feature 0x02 3 0 0 0-4, 129- 136 0 0 0 endpoint halt set_address 0x00 5 addr 0 0 0 0 0 get_descriptor 0x80 6 0 1 0 0 len lsb len msb device descriptor get_descriptor 0x80 6 0 2 0 0 len lsb len msb configuration descriptor get_configuration 0x80 8 0 0 0 0 1 0 set_configuration 0x00 9 n 0 0 0 0 0 get_interface 0x81 10 0 0 0-7 0 1 0 cdc_acm_if set_line_coding 0x21 32 0 0 0, 2, 4, 6 0 7 0 set the uart baud rate, parity, stop bits, etc. cdc_acm_if get_line_coding 0xa1 33 0 0 0, 2, 4, 6 0 7 0 get the uart baud rate, parity, stop bits, etc. cdc_acm_if set_control_line_state 0x21 34 val 0 0, 2, 4, 6 0 0 0 set uart control lines
xr21v1410 12 1-ch full-speed usb uart rev. 1.3.0 2.1 uart block numbers the table below lists the block numbers for accessi ng each of the uart channels and the uart manager.. cdc_acm_if send_break 0x21 35 val lsb val msb 0, 2, 4, 6 0 0 0 send a break for the speci- fied duration xr_set_reg 0x40 0 val 0 regis- ter block 0 0 exar custom command: set one 8-bit register val: 8-bit register value register address: see table 7 block number: see table 5 xr_getn_reg 0xc0 1 0 0 regis- ter block count lsb count msb exar custom register: get count 8-bit registers register address: see table 7 block number: see table 5 t able 5: c ontrol b locks b lock n ame b lock n umber d escription uart 0 the configuration and control registers for th e uart. uart manager 4 the control registers for the uart man ager. the uart manager enables/disables the tx and rx fifos for each uart. uart custom 0x66 custom uart control registers. enab les / disables for wide mode, low latency mode and custom interrupt packet. t able 4: s upported usb c ontrol c ommands n ame r equest t ype r equest v alue i ndex l ength d escription
xr21v1410 13 rev. 1.3.0 1-ch full-speed usb uart 3.0 register set description the internal register set of the v1410 consists of 3 different blocks of registers: the uart manager, uart registers and uart miscellaneous registers. the ua rt manager controls the tx and rx enables and fifos of all uart channels. the uart registers configure and control the remaining uart channel functionali ty with the exception of low latency mode, wide mode and custom interrupt packet enables in the uart cus tom register block. registers are accessed only via the usb interface b y the xr_set_reg and xr_get_reg commands listed in table 4 . the register address offsets are given in table 6 , table 7 and table 15 , and the register blocks are given in table 5 . 3.1 uart manager registers 3.1.1 fifo_enable registers enables the rx fifo and tx fifos. for proper funct ionality, the uart tx and rx must be enabled in the following order: fifo_enable = 0x1 // enable tx fifo uart_enable = 0x3 // enable tx and rx fifo_enable = 0x3 // enable rx fifo 3.1.2 rx_fifo_reset and tx_fifo_reset registers writing a non-zero value to these registers resets the fifos. t able 6: uart m anager r egisters a ddress r egister n ame b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 0x10 fifo_enable 0 0 0 0 0 0 rx tx 0x18 rx_fifo_reset bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit- 1 bit-0 0x1c tx_fifo_reset bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit- 1 bit-0
xr21v1410 14 1-ch full-speed usb uart rev. 1.3.0 3.2 uart register map t able 7: uart r egisters a ddress r egister n ame b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 0x00 reserved 0 0 0 0 0 0 0 0 0x01 reserved 0 0 0 0 0 0 0 0 0x02 reserved 0 0 0 0 0 0 0 0 0x03 uart_enable 0 0 0 0 0 0 rx tx 0x04 clock_divisor0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit -1 bit-0 0x05 clock_divisor1 bit-15 bit-14 bit-13 bit-12 bit-11 bit -10 bit-9 bit-8 0x06 clock_divisor2 0 0 0 0 0 bit-18 bit-17 bit-16 0x07 tx_clock_mask0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit -1 bit-0 0x08 tx_clock_mask1 bit-15 bit-14 bit-13 bit-12 bit-11 bit -10 bit-9 bit-8 0x09 rx_clock_mask0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit -1 bit-0 0x0a rx_clock_mask1 bit-15 bit-14 bit-13 bit-12 bit-11 bit -10 bit-9 bit-8 0x0b character_format stop parity data bits 0x0c flow_control 0 0 0 0 half- duplex flow control mode select 0x0d reserved 0 0 0 0 0 0 0 0 0x0e reserved 0 0 0 0 0 0 0 0 0x0f reserved 0 0 0 0 0 0 0 0 0x10 xon_char bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit- 0 0x11 xoff_char bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit -0 0x12 loopback_ctl 0 0 0 0 0 en 0 0 0x13 error_status break status overrun error parity error framing error break error 0 0 0 0x14 tx_break bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit- 0 0x15 xcvr_en_delay 0 0 0 0 delay 0x16 reserved 0 0 0 0 0 0 0 0 0x17 reserved 0 0 0 0 0 0 0 0 0x18 reserved 0 0 0 0 0 0 0 0 0x19 reserved 0 0 0 0 0 0 0 0 0x1a gpio_mode 0 0 0 0 xcvr enable polarity mode select 0x1b gpio_direction 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x1c gpio_int_mask 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x1d gpio_set 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x1e gpio_clear 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x1f gpio_status 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0
xr21v1410 15 rev. 1.3.0 1-ch full-speed usb uart 3.3 uart register descriptions all register bits default to a value of 0 unless otherwise noted. 3.3.1 uart_enable register description (read/write) this register enables the uart tx and rx. for prop er functionality, the uart tx and rx must be enable d in the following order: fifo_enable = 0x1 // enable tx fifo uart_enable = 0x3 // enable tx and rx of that channe l fifo_enable = 0x3 // enable rx fifo uart_enable[0]: enable uart tx logic 0 = uart tx disabled. logic 1 = uart tx enabled. uart_enable[1]: enable uart rx logic 0 = uart rx disabled. logic 1 = uart rx enabled. uart_enable[7:2]: reserved these bits are reserved and should remain 0. 3.3.2 clock_divisor0, clock_divisor1, clock_divisor2 register description (read/write) these registers are used for programming the baud r ate. the v1410 uses a 19-bit divisor and 16-bit ma sk register. using the internal 48mhz oscillator, the 19-bit divisor is calculated as follows: clock_divisor = trunc ( 48000000 / baud rate ) for example, if the the baud rate is 115200bps, the n clock_divisor = trunc ( 48000000 / 115200 ) = trunc (416.66667) = 416 clock_divisor0[7:0]: baud rate clock divisor bits [ 7:0] clock_divisor1[7:0]: baud rate clock divisor bits [ 15:8] clock_divisor2[2:0]: baud rate clock divisor bits [ 18:16] clock_divisor2[7:3]: reserved these bits are reserved and should remain 0. 3.3.3 tx_clock_mask0, tx_clock_mask1 register descri ption (read/write) a look-up table is used for the value of the 16-bit tx clock mask registers. the index of the look-up table is calculated as follows: index = trunc ( ( ( 48000000 / baud rate ) - clock _divisor ) * 32) for example, if the baud rate is 115200bps, then th e index will be: index = trunc ( ( ( 48000000 / 115200 ) - 416 ) * 32) = trunc (21.3333) = 21 the values for some baud rates to program the tx_cl ock_mask registers are listed in table 8 . for baud rates that are not listed, use the index to select tx_clock_mask register values from table 9 . 3.3.4 rx_clock_mask0, rx_clock_mask1 register descri ption (read/write) the values for some example baud rates to program t he rx_clock_mask registers are listed in table 8 . for baud rates that are not listed, use the same in dex calculated for the tx_clock_mask register to se lect rx_clock_mask register values from table 9 .
xr21v1410 16 1-ch full-speed usb uart rev. 1.3.0 for baud rates that are not listed in the table abo ve, use the index value calcuated using the formula in section 3.3.3, tx_clock_mask0, tx_clock_mask1 regi ster description (read/write) on page 15 to determine which tx clock and rx clock mask regis ter values to use from table 9 . for the the rx clock mask register, there are 2 values listed and would depend on whether the clock divisor is even or odd. for even clock divisors, use the value from the first c olumn. for odd clock divisors, use the value from the last column. t able 8: c lock d ivisor and c lock m ask v alues for c ommon b aud r ates b aud r ate ( bps ) c lock d ivisor (d ecimal ) tx c lock m ask (h ex ) rx c lock m ask (h ex ) 1200 40000 0x0000 0x0000 2400 20000 0x0000 0x0000 4800 10000 0x0000 0x0000 9600 5000 0x0000 0x0000 19200 2500 0x0000 0x0000 38400 1250 0x0000 0x0000 57600 833 0x0912 0x0924 115200 416 0x0b6d 0x0b6a 230400 208 0x0912 0x0924 460800 104 0x0208 0x0040 500000 96 0x0000 0x0000 576000 83 0x0912 0x0924 921600 52 0x0040 0x0000 1000000 48 0x0000 0x0000 1152000 41 0x0b6d 0x0db6 1500000 32 0x0000 0x0000 2000000 24 0x0000 0x0000 2500000 19 0x0104 0x0108 3000000 16 0x0000 0x0000 3125000 15 0x0492 0x0492 3500000 13 0x076d 0x0bb6 4000000 12 0x0000 0x0000 4250000 11 0x0122 0x0224 6250000 7 0x0b6d 0x0db6 8000000 6 0x0000 0x0000 12000000 4 0x0000 0x0000
xr21v1410 17 rev. 1.3.0 1-ch full-speed usb uart t able 9: tx and rx c lock m ask v alues i ndex (d ecimal ) tx c lock m ask (h ex ) rx c lock m ask (h ex ) - e ven c lock d ivisor rx c lock m ask (h ex ) - o dd c lock d ivisor 0 0x0000 0x0000 0x0000 1 0x0000 0x0000 0x0000 2 0x0100 0x0000 0x0100 3 0x0020 0x0400 0x0020 4 0x0010 0x0100 0x0010 5 0x0208 0x0040 0x0208 6 0x0104 0x0820 0x0108 7 0x0844 0x0210 0x0884 8 0x0444 0x0110 0x0444 9 0x0122 0x0888 0x0224 10 0x0912 0x0448 0x0924 11 0x0492 0x0248 0x0492 12 0x0252 0x0928 0x0292 13 0x094a 0x04a4 0x0a52 14 0x052a 0x0aa4 0x054a 15 0x0aaa 0x0954 0x04aa 16 0x0aaa 0x0554 0x0aaa 17 0x0555 0x0ad4 0x05aa 18 0x0b55 0x0ab4 0x055a 19 0x06b5 0x05ac 0x0b56 20 0x05b5 0x0d6c 0x06d6 21 0x0b6d 0x0b6a 0x0db6 22 0x076d 0x06da 0x0bb6 23 0x0edd 0x0dda 0x076e 24 0x0ddd 0x0bba 0x0eee 25 0x07bb 0x0f7a 0x0dde 26 0x0f7b 0x0ef6 0x07de 27 0x0df7 0x0bf6 0x0f7e 28 0x07f7 0x0fee 0x0efe 29 0x0fdf 0x0fbe 0x07fe 30 0x0f7f 0x0efe 0x0ffe 31 0x0fff 0x0ffe 0x0ffd
xr21v1410 18 1-ch full-speed usb uart rev. 1.3.0 3.3.5 character_format register description (read/wr ite) this register controls the character format such as the word length (7, 8 or 9), parity (odd, even, fo rced 0, or forced 1) and number of stop bits (1 or 2). character_format[3:0]: data bits . all other values for character_format[3:0] are rese rved. character_format[6:4]: parity mode select these bits select the parity mode. if 9-bit data m ode has been selected, then writing to these bits w ill not have any effect. in other words, there will not be an a dditional parity bit. character_format[7]: stop bit select this register selects the number of stop bits to ad d to the transmitted character and how many stop bi ts to check for in the received character. 3.3.6 flow_control register description (read/write) these registers select the flow control mode. thes e registers should only be written to when the uart is disabled. writing to the flow_control register whe n the uart is enabled will result in undefined behavior. note that the flow_control register sett ings are used in conjunction with the gpio_mode register. t able 10: d ata b its d ata b its character_format[3:0] 7 0111 8 1000 9 1001 t able 11: p arity s election b it -6 b it -5 b it -4 p arity selection 0 0 0 no parity 0 0 1 odd parity 0 1 0 even parity 0 1 1 force parity to mark, 1 1 0 0 force parity to space, 0 t able 12: s top b it s election b it -7 n umber of s top b its 0 1 stop bit 2 2 stop bits
xr21v1410 19 rev. 1.3.0 1-ch full-speed usb uart flow_control[2:0]: flow control mode select flow_control[3]: half-duplex mode logic 0 = normal (full-duplex) mode. the uart can transmit and receive data at the same time. logic 1 = half-duplex mode. in half-duplex mode, a ny data on the rx pin is ignored when the uart is transmitting data. flow_control[7:4]: reserved these bits are reserved and should remain 0. 3.3.7 xon_char, xoff_char register descriptions (rea d/write) the xon_char and xoff_char registers store the xon and xoff characters, respectively, that are used in the automatic software flow control. if the v14 10 is configured in multidrop mode, the xon_char an d xoff_char registers are instead used for address ma tching. xon_char[7:0]: xon character in automatic software flow control mode, the uart w ill resume data transmission when the xon character has been received. for behavior in the address match mode, see section 1.5.7, multidrop mode with address matchin g on page 9 . xoff_char[7:0]: xoff character in automatic software flow control mode, the uart w ill suspend data transmission when the xoff charact er has been received. for behavior in the address match mode, see section 1.5.7, multidrop mode with address matchin g on page 9 . 3.3.8 loopback_ctl register descriptions (read/wri te) loopback_ctl[1:0]: reserved these bits are reserved and should remain 0. loopback_ctl[2]: enable logic 0 = internal uart (tx to rx) loopback is disa bled. logic 1 = internal uart (tx to rx) loopback is enab led. loopback_ctl[7:3]: reserved these bits are reserved and should remain 0. t able 13: f low c ontrol m ode s election m ode b it -2 b it -1 b it -0 m ode d escription 0 0 0 0 no flow control, no address matching. 1 0 0 1 hw flow control enabled. auto rts/cts or dtr/d sr must be selected by gpio_mode. 2 0 1 0 sw flow control enabled 3 0 1 1 multidrop mode - rx only after address match, t x independent. (typically used with gpio_mode 3) 4 1 0 0 multidrop mode - rx / tx only after address mat ch. (typically used with gpio_mode 4)
xr21v1410 20 1-ch full-speed usb uart rev. 1.3.0 3.3.9 error_status register description - read-only this register reports any errors that may have occu rred on the line such as break, framing, parity and overrun. error_status[2:0]: reserved these bits are reserved. any values read from thes e bits should be ignored. error_status[3]: break error logic 0 = no break condition logic 1 = a break condition has been detected (clea rs after read). error_status[4]: framing error logic 0 = no framing error logic 1 = a framing error has been detected (clears after read). a framing error occurs when a stop b it is not present when it is expected. error_status[5]: parity error logic 0 = no parity error logic 1 = a parity error has been detected (clears after read). error_status[6]: overrun error logic 0 = no overrun error logic 1 = an overrun error has been detected (clear s after read). an overrun error occurs when the rx fifo is full and another byte of data is received. error_status[7]: break status logic 0 = break condition is no longer present. logic 1 = break condition is currently being detect ed. 3.3.10 tx_break register description (read/write) writing a non-zero value to this register causes a break condition to be generated continuously until the register is cleared. if data is being shifted out of the tx pin, the data will be completely shifted out before the break condition is generated. 3.3.11 xcvr_en_delay register description (read/writ e) xcvr_en_delay[3:0]: turn-around delay this is the number of bit times to wait before chan ging the direction of the transceiver from transmit to receive when half-duplex mode is enabled. xcvr_en_delay[3:0]: reserved these bits are reserved and should be 0.
xr21v1410 21 rev. 1.3.0 1-ch full-speed usb uart 3.3.12 gpio_mode register description (read/write) gpio_mode[2:0]: gpio mode select there are 4 modes of operation for the gpios. the d escriptions can be found in section 1.5, uart on page 7 . gpio_mode[3]: transceiver enable polarity logic 0 = gpio5 low for tx logic 1 = gpio5 high for tx gpio_mode[7:4]: reserved these register bits are reserved. when writing to these bits, the value should be 0. when reading from these bits, they are undefined and should be ignored. 3.3.13 gpio_direction register description (read/wri te) this register controls the direction of the gpio if it is not controlled by the gpio_mode register. gpio_direction[5:0]: gpiox direction logic 0 = gpiox is an input. logic 1 = gpiox is an output. gpio_direction[7:6]: reserved these register bits are reserved and should be 0. 3.3.14 gpio_int_mask register description (read/writ e) enables / disables generation of a usb interrupt pa cket at the change of state of gpio pins when they are configured as inputs. gpio_int_mask[5:0]: gpiox interrupt mask logic 0 = a change on this input causes the device to generate an interrupt packet. logic 1 = a change on this input does not cause the device to generate an interrupt packet. gpio_int_mask[7:6]: reserved these register bits are reserved and should be 0. t able 14: gpio m odes bits [2:0] gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 m ode d escription 000 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio mode, all gpi o pins available as gpio 001 gpio0 gpio1 gpio2 gpio3 cts# rts# gpio4 and gpio5 used for auto rts/cts hw flow control 010 gpio0 gpio1 dsr# dtr# gpio4 gpio5 gpio2 and gpio3 used for auto dtr/dsr hw flow control 011 gpio0 gpio1 gpio2 gpio3 gpio4 xcvr enable gpio5 used for auto transceiver enable during transmit 100 gpio0 gpio1 gpio2 gpio3 gpio4 xcvr enable gpio5 used for auto transceiver enable after address match (see flow_control mode 4).
xr21v1410 22 1-ch full-speed usb uart rev. 1.3.0 3.3.15 gpio_set register description (read/write) writing a 1 in this register drives the gpio outp ut high. writing a 0 to a bit has no effect. bi ts 7-6 are unused and should be 0. 3.3.16 gpio_clear register description (read/write) writing a 1 in this register drives the gpio outp ut low. writing a 0 to a bit has no effect. bit s 7-6 are unused and should be 0. 3.3.17 gpio_status register description (read-only) this register reports the current state of the gpio pin. 3.4 uart custom registers.. 3.4.1 custom register description (read/write) this register controls the bmaxpacketsize and enabl es the wide mode functionality for the uart. custom[0]: enable wide mode logic 0 = normal (7, 8 or 9 bit data) mode logic 1 = wide mode - see section 1.5.1.1, wide mode transmit on page 7 and section 1.5.2.1, wide mode receive on page 7 custom[1]: max packet size logic 0 = bmaxpacketsize = 64 bytes logic 1 = bmaxpacketsize = 63 bytes (this bit is au tomatically set to 1 if the xr21v1410 receives a cdc_acm usb command) custom[7:2]: reserved these bits are reserved and should remain 0 3.4.2 low_latency register description (read/write) this register is automatically set to logic 1 for baud rates below 46921 bps, and can be manually se t for baud rates of 46921 bps and higher. this register enabl es the low latency feature of the uart. write to t his register following any desired baud rate setting ch ange. low_latency[0]: enable low latency mode logic 0 = receive data is not forwarded from the rx fifo until bmaxpacketsize (64 bytes) or timeout (3 characters) has occurred. logic 1 = all data in the rx fifo is provided to th e usb host at the next bulk in request irrespective of the number of bytes in the fifo. low_latency[7:1]: reserved these bits are reserved and should remain 0. t able 15: uart c ustom r egisters a ddress r egister n ame b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 0x03 custom 0 0 0 0 0 0 maxpkt- size wide_ en 0x04 low_latency 0 0 0 0 0 0 0 en 0x06 custom_int_packet 0 gpio5 gpio4 gpio3 gpio0 0 gpio2 gpi o1
xr21v1410 23 rev. 1.3.0 1-ch full-speed usb uart 3.4.3 custom_int_packet (read/write) this register is used to enable / disable gpio stat us in the high data byte of the custom interrupt pa cket. see table 16, interrupt packet format, on page 24 and table 18, data field of customized interrupt packet - exar vendor specific, on page 25 . custom_int_packet[0]: gpio1 logic 0 = disable gpio1 status in custom interrupt packet. logic 1 = enable gpio1 status in custom interrupt p acket. custom_int_packet[1]: gpio2 logic 0 = disable gpio2 status in custom interrupt packet. logic 1 = enable gpio2 status in custom interrupt p acket. custom_int_packet[2]: reserved this bit is reserved and should remain 0. custom_int_packet[3]: gpio0 logic 0 = disable gpio0 status in custom interrupt packet. logic 1 = enable gpio0 status in custom interrupt p acket. custom_int_packet[4]: gpio3 logic 0 = disable gpio3 status in custom interrupt packet. logic 1 = enable gpio3 status in custom interrupt p acket. custom_int_packet[5]: gpio4 logic 0 = disable gpio4 status in custom interrupt packet. logic 1 = enable gpio4 status in custom interrupt p acket. custom_int_packet[6]: gpio5 logic 0 = disable gpio5 status in custom interrupt packet. logic 1 = enable gpio5 status in custom interrupt p acket. custom_int_packet[7]: reserved this bit is reserved and should remain 0.
xr21v1410 24 1-ch full-speed usb uart rev. 1.3.0 t able 16: i nterrupt p acket f ormat t able 17: d ata f ield of s tandard i nterrupt p acket if the exar vendor specific packet mapping is enabl ed then the data field also includes status for all of the uart / gpio pins as follows: o ffset f ield s ize (b ytes ) v alue d escription 0 bmrequesttype 1 8b10100001 d7 = device-to-host direc tion d6:5 = class type d4-0: = interface recipient 1 bnotification 1 8h20 defined encoding for serial_sta te 2 wvalue 2 16h0000 4 windex 2 16h0000 d15-8 = reserved (0) d7-0 = interface number, 8h00 for the cdc com- mand interface 6 wlength 2 16h0002 2 bytes of transferred data 8 data 2 standard int_status (see table 17 or table 18 ) d15-7 = reserved (0) d6 = boverrun d5 = bparity d4 = bframing d3 = bringsignal (ri) d2 = bbreak d1 = btxcarrier (dsr) d0 = brxcarrier (cd) b it ( s ) f ield d escription d15..d7 reserved (0) d6 boverrun received data has been discarded due to o verrun in the device. d5 bparity a parity error has occured. d4 bframing a framing error has occured. d3 bringsignal state of ring signal detection of the device. d2 bbreak state of break detection mechanism of the d evice. d1 btxcarrier state of transmission carrier. this si gnal corresponds to v.24 signal 106 and rs-232 signal dsr. d0 brxcarrier state of receiver carrier detection mec hanism of device. this signal corre- sponds to v.24 signal 109 and rs-232 signal dcd.
xr21v1410 25 rev. 1.3.0 1-ch full-speed usb uart t able 18: d ata f ield of c ustomized i nterrupt p acket - e xar v endor s pecific b it ( s ) f ield d escription 15 d15 reserved (0) 14 d14 bgpio5 (rts) 13 d13 bgpio4 (cts) 12 d12 bgpio3 (dtr) 11 d11 bgpio0 (ri) 10 d10 reserved (0) 9 d9 bgpio2 (dsr) 8 d8 bgpio1 (cd) 7 d7 reserved (0) 6 d6 boverrun 5 d5 bparity 4 d4 bframing 3 d3 bringsignal (ri) 2 d2 bbreak 1 d1 btxcarrier (dsr) 0 d0 brxcarrier (cd)
xr21v1410 26 1-ch full-speed usb uart rev. 1.3.0 4.0 electrical characteristics dc electrical characteristics - power consumption u nless otherwise noted : ta = -40 o to +85 o c, v cc is 2.97 to 3.63v s ymbol p arameter l imits 3.3v m in typ m ax u nits c onditions i cc power supply current 16 20 ma i susp suspend mode current 1.5 1.65 ma dc electrical characteristics - uart, lowpower & gp io pins u nless otherwise noted : ta = -40 o to +85 o c, v cc is 2.97 to 3.63v s ymbol p arameter l imits 3.3v m in m ax u nits c onditions v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage 0.3 v i ol = 4 ma v oh output high voltage 2.2 v i oh = -4 ma i il input low leakage current 10 ua i ih input high leakage current 10 ua c in input pin capacitance 5 pf dc electrical characteristics - usb i/o pins u nless otherwise noted : ta = -40 o to +85 o c, v cc is 2.97 to 3.63v s ymbol p arameter l imits 3.3v m in m ax u nits c onditions v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage 0 0.3 v external 15 k ohm to gnd on usbd- pin v oh output high voltage 2.8 3.6 v external 15 k ohm to gnd on usbd- pin v drvz driver output impedance 28 44 ohms i osc open short current current 38.5 ma 1.5 v on usbd+ and usbd-
xr21v1410 27 rev. 1.3.0 1-ch full-speed usb uart package dimensions (16 pin qfn - 3 x 3 x 0.9 mm ) note: the control dimension is the millimeter colum n inches millimeters symbol min max min max a 0.031 0.035 0.80 0.90 a1 0.000 0.002 0.00 0.05 a3 0.000 0.008 0.00 0.20 d 0.114 0.122 2.90 3.10 d2 0.065 0.069 1.65 1.75 b 0.008 0.012 0.20 0.30 e 0.0197 bsc 0.50 bsc l 0.010 0.014 0.25 0.35 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm
28 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar co rporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representa tion that the circuits are free of patent infringement. chart s and schedules contained here in are only for illu stration purposes and may vary depending upon a users speci fic application. while the information in this publ ication has been carefully checked; no responsibility, howe ver, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonabl y be expected to cause failure of the life support system or to significantly affect its safety or effectiveness . products are not authorized for use in such appli cations unless exar corporation receives, in writing, assurances t o its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; (c) potential liability of exar corporation is ad equately protected under the circumstances. copyright 2012 exar corporation datasheet april 2012. send your uart technical inquiry with technical det ails to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. xr21v1410 1-ch full-speed usb uart rev. 1.3.0 revision history d ate r evision d escription june 2009 1.0.0 released datasheet september 2010 1.1.0 clarified pin functionality, wid e mode and low latency mode including registers / blocks, clarified flow_control and gpio_mode regist er functionality. april 2011 1.2.0 updated ordering information, sda/sc l pin types, modified gpio0 pin name and added loopback_ctl register and description. april 2012 1.3.0 updated lowpower pin description, bm axpacketsize and dc electrical charac- terisitics. see pcn12-0305-01 for more details.

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